A new hybrid non-linear model, mixing neuron networks and equivalent scheme has been developed. The model combines the advantages of the two approaches. Indeed, the neuron part allows the electrical characteristics description with good accuracy and low calculation time. While the equivalent scheme part allows the scale laws and the intrinsic model. This model is a good trade off between high adaptability (neuron network) and comprehensive form of topology (current source, capacitors, inductors, resistances, schottky contact ...), in fact all elements in the model have electrical signification.
Model principle
The model principle is to take into account the intrinsics elements of the equivalent diagram with a neuron network and the current source with a second one.
Cgs, Cgd and Cds capacitances and Rgs resistance as well are represented by a neurons network according to the Vgsii and Vdsii voltages (see figure bellow). The gm transconductance and the gd conductance are represented by a second neuron network describing the drain current Id according to Vgstii and Vdsii, with Vgstii=Vgsii*exp(-j*w *τ) in order to take into account the delay between the gate-source field and the channel conductance (τ). The other intrinsic elements of the equivalent diagram are considered as constant or null for all biasing conditions.
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Diagram representing two distinct neurons network. These ones allow the evolutions of the intrinsic elements and the IV characteristics modelling. |
To include the extracted capacitances into the model, without determining the charge equations, the time derivatives of the intrinsic voltages are determined. The current crossing the capacitances can then be written with the time derivative Iij=Cij*dVij/dt. The conduction current of gate-source and gate-drain diodes are added to the displacement currents related to their respective capacitances, so that the diodes and capacitances are in parallel.
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Intrinsic part of the equivalent diagram based on neurons networks. Capacitances, rgs and rgd resistances can be considered in a non-linear way. The temperature and quiescent voltages influence the access resistances of the device. |
The extrinsic elements of the equivalent diagram are fixed, except access resistances which vary according to the dissipated power and/or to the quiescent bias point. The temperature, used in the equivalent diagram of the transistor, is calculated using a SDD and a Rth-Cth dipole. The temperature is also used to vary the drain current if necessary, and it would be possible to re-use the temperature to change the values of the transistor intrinsic elements. The reactive extrinsic elements (capacitances and inductances) are used to take into account coplanar access lines and pad geometry. The extrinsic diagram (see figure below) can be used for other intrinsic models for which temperature information is necessary.
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General implementation of the equivalent diagram model of FETs with taking into account of the temperature in the intrinsic model |
Model validationTo confirm the modelling approach validity, various comparisons between measurements and simulations are shown. These comparisons include static characteristics, pulsed characteristics and small and large signal characteristics. Furthermore the model precision compared to measurements is evaluated regarding the simulation time as well as robustness model.
The first test is to compare the model with measurements within static mode. This test shows the ability, for a high frequency power devices, to describe the quiescent biasing point with accuracy. The figure below shows the comparison between measurements and the model.
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DC comparison, symbols are used for measurements and lines for model.· |
One notes a good agreement between measurements and simulations.
The second test compares the model with measurements within pulsed mode. This comparison shows the ability of the model to describe the I-V characteristics when the quiescent bias point is fixed. The figure below shows the comparison between measurements and the model in pulsed regime for two quiescent biasing points.
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static pulsed comparison. Vgs0= -5V and Vds0=20V, |
The next step is the small signal characteristics comparison. Sij or Yij parameters allow the comparison at high frequency. The figure below presents the comparison between measurements (blue) and simulation (red) for the quiescent bias point Vgs0= -5V and Vds0=20V, and for Vgsi=-6V and Vdsi=2 to 20V with 2V step.
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Comparison in pulsed mode. Vgs0= -5V and Vds0=20V, Vgsi=-6V and Vdsi=2 to 20V with 2V step. Blue lines are used for measurements and red lines for model. |
A very good correlation can be noted between measurements and simulation for the entire instantaneous bias voltage range
The large signal comparison is performed with a large signal vector network analyser measurement setup allowing the study both in time and frequency domains. The measured frequency spectrum is whithin the range 1-20GHz. Since the fundamental frequency is 4GHz, the 2nd, 3rd, 4th and 5th harmonics are available. The simulation has been carried out with the same conditions (F0=4GHz and NumberOfHarmonics=5). The figure below presents the comparison between measured and simulated power performances for the bias points Vgs0= -5V and Vds0=20V.
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Power performance comparison (a) and harmonic performances comparison (b). Vgs0= -5V and Vds0=20V. Symbols are used for measurements and lines for model. |
The figure below presents the time evolution comparison for the same conditions (bias, load and harmonics) than previously. The extrinsic gate and drain measured voltages and current (v1mts and v2mts), (i1mts and i2mts), are compared to the simulated ones. The model describes the measurements with a good accuracy.
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Time domain comparison. Vgs0= -5V and Vds0=20V. Symbols are used for measurements and lines for model |
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Load lines comparison in extrinsic (a) and intrinsic (b) tips. Vgs0= -5V and Vds0=20V, Vgsi=-6V and Vdsi=2 to 20V with 2V step. Symbols are used for measurements and lines for model. |
f1=3.995GHz, f2=4.005GHz (spacing 10MHz). Zload=41+j*28Ω around 4GHz, Zload=50 Ω for other frequencies. Number of harmonics for f1 and f2=7, max_imd_order=7. Simulation time=9.5sec. Figure below presents a 2-tones simulation with the evolution of harmonics around the carrier at the first, third and fifth orders
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Two tones simulation. f1 and f2 are in red, 2*f1-f2 and 2*f2-f1 are in blue and 3f1-2*f2 and 3*f2-2*f1 are in green. |
Convergence speed and scalability
For the speed test, the setup is: f0=4GHz, Zload=41.4+j*28.4Ω at 4GHz and Zload=50 Ω for other frequencies; Number of harmonics=15 and Pinc=-5 to 26dBm with 0.5dBm step.
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Test in harmonic balance. Vgs0= -5V and Vds0=20V. Simulation time=2.4s. The simulation speed is very good with 2.4s for this setup. |
For the robustness test, Pinc=-5 to 15dBm with 2.5dBm step and 16 to 45dBm with 1dBm step.
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Robustness test in harmonic balance. The conditions are the same than the previous chart and the simulation time is 16.7s. |
The robustness of the model has been tested for more than 30dB compression with 1dB step. For the last five points, the convergence is more difficult due to the gate current explosion (900mA for the last point). Therefore, the total simulation time is 16.7s with a personal computer AMD ATHLON 2500+ and 2GB RAM PC3200 (running with Windows XP SP2 environment). The 20dB compression point is obtained for 4.8s simulation time.
Scalling laws have been established for the device under study. These laws have been applied to all intrinsic elements and to thermal behaviour.
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Comparison of small signal performances for different total gate width from 200µm to 800µm with 100µm step.
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Comparison of power performances for different total gate width from 200µm to 800µm with 100µm step. The output impedance has been considered (a) constant (41.4+j*28.4) and (b) inversly proportional to the total gate width.
